1. Field of the Invention
The invention relates to methods of fabricating semiconductor integrated circuit devices and semiconductor integrated circuit devices fabricated thereby and, more particularly, to methods of fabricating semiconductor integrated circuit devices with thin film transistors using a selective epitaxial growth (SEG) technique and a partial planarization technique, and semiconductor integrated circuit devices fabricated thereby.
2. Description of the Related Art
Semiconductor integrated circuits employ discrete devices, such as metal oxide semiconductor (MOS) transistors, as switching devices. Most of the MOS transistors are directly formed in a semiconductor substrate. That is, the MOS transistors are formed to have channel regions and source/drain regions in the semiconductor substrate. In this case, the MOS transistors may be referred to as bulk MOS transistors.
When the semiconductor integrated circuits employ bulk MOS transistors, there is a limitation in improving integration density of the semiconductor integrated circuits. In particular, when the semiconductor integrated circuits are complementary MOS (CMOS) circuits composed of N-channel bulk MOS transistors and P-channel bulk MOS transistors, it is more difficult to improve the integration density of the semiconductor integrated circuits due to a latch-up phenomenon that occurs in the CMOS circuit.
In recent years, in order to solve the issues of the latch-up phenomenon as well as the integration density of the semiconductor integrated circuits, thin film transistors stacked on the semiconductor substrate are widely used. For example, the thin film transistors are used in a unit cell of a static random access memory (SRAM). The SRAM may offer advantages of lower power consumption and faster operating speed as compared to a dynamic RAM (DRAM). Accordingly, the SRAM is widely used in portable appliances or as a cache memory device of a computer.
A unit cell of the SRAM is typically categorized as either a resistor-load SRAM cell or a complementary metal oxide semiconductor (CMOS) SRAM cell. The resistor-load SRAM cell employs a high resistor as the load device, and the CMOS SRAM cell employs a p-channel MOS transistor as the load device. The CMOS SRAM cell is also classified into two types: a thin film transistor (TFT) SRAM cell that employs the TFT as the load device, and a bulk CMOS SRAM cell that employs the bulk MOS transistor as the load device.
The bulk CMOS SRAM cell exhibits high cell stability as compared to the TFT SRAM cell and the resistor-load SRAM cell. In other words, the bulk CMOS SRAM cell shows excellent low voltage characteristics and low stand-by current. This is because all of the transistors constituting the bulk CMOS SRAM cell are formed at a single-crystalline silicon substrate whereas the TFTs of the TFT SRAM cell are typically formed using a polysilicon layer as a body layer. However, the bulk CMOS SRAM cell shows low integration density as well as weak latch-up immunity as compared to the TFT SRAM cell. Accordingly, in order to realize a highly integrated SRAM having high reliability, it is required to continuously improve the characteristic of the load transistors employed in the TFT SRAM cell.
In the meantime, semiconductor devices having the TFTs stacked over a semiconductor substrate are disclosed in U.S. Pat. No. 6,022,766 to Chen et al., entitled “Semiconductor Structure Incorporating Thin Film Transistors and Methods for its Manufacture”. According to Chen et al., a conventional bulk MOS transistor is formed at a single-crystalline silicon substrate, and a TFT is stacked over the bulk MOS transistor. One of the source/drain regions of the bulk MOS transistor is electrically coupled to one of the source/drain regions of the TFT through a metal plug such as a tungsten plug. Therefore, when the bulk MOS transistor and the TFT are an NMOS transistor and a PMOS transistor, respectively, the bulk MOS transistor has an ohmic contact with the TFT through the metal plug.
Furthermore, a body layer of the TFT is formed by depositing an amorphous silicon layer on the semiconductor substrate having the metal plug and by crystallizing the amorphous silicon layer through an annealing process. In this case, the body layer corresponds to a polysilicon layer having large grains. That is, it is difficult to transform the body layer to a perfect single-crystalline silicon layer. In conclusion, it is difficult to form the TFT having excellent electrical characteristics that correspond to that of the bulk MOS transistor. Thus, methods for improving the characteristics of the TFT stacked over the semiconductor substrate are continuously required.